I am a former member of the
SCALE group, which was
part of the Department of Electrical Engineering
and Computer Science at the Massachusetts Institute of Technology.
My advisor was Professor
Krste Asanović.
Research
My research interests include exception handling mechanisms,
energy-exposed
instruction sets, and compilation techniques for novel architectures.
My doctoral thesis work focused
on using compile-time
information to implement low-overhead exception handling approaches
in parallel architectures. As a component of my thesis, I also conducted
research on compiling for
vector-thread
architectures, which can flexibly target multiple forms of parallelism.
Publications
Many of these papers are copyright of
the respective journal or conference organizing body. These online
copies are provided for your personal research use only.
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"Compiling for Vector-Thread Architectures"
Mark Hampton and Krste Asanović
2008 International Symposium on Code Generation and Optimization
(CGO), Boston, MA, April 2008.
[ PDF
| conference ]
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"Reducing Exception Management Overhead with Software Restart Markers"
Mark Hampton
Ph.D. Thesis, Massachusetts Institute of Technology, February 2008.
[ PDF
]
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"The Academy of Courageous Minority Engineers: A Model for Supporting
Minority Graduate Students in the Completion of Science and Engineering
Degrees"
Eric Brittain, Reginald Bryant, Lincoln Chandler, Robbin Chapman, Shaundra
Daily, Mark Hampton, Ishara Mills-Henry, and Aisha Walcott
114th Annual American Society for Engineering Education Conference &
Exposition, Honolulu, HI, June 2007.
[ PDF
| conference ]
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"Implementing Virtual Memory in a Vector Processor with Software
Restart Markers"
Mark Hampton and Krste Asanović
20th ACM International Conference on Supercomputing (ICS06),
Cairns, Australia, June 2006.
[ PDF
| conference ]
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"The Vector-Thread Architecture"
Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian
Pharris, Jared Casper, and Krste Asanović
IEEE Micro Special Issue: Micro's Top Picks from Computer
Architecture Conferences, November/December 2004.
(Abridged version of ISCA 2004 paper)
[ PDF
| magazine ]
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"The Vector-Thread Architecture"
Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian
Pharris, Jared Casper, and Krste Asanović
31st International Symposium on Computer Architecture (ISCA-31),
Munich, Germany, June 2004.
[ PDF
| conference ]
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"Energy-Exposed Instruction Sets"
Krste Asanović, Mark Hampton, Ronny Krashinsky, and Emmett Witchel
Power Aware Computing, ed. by R. Graybill and R. Melhem,
Kluwer Academic/Plenum Publishers, Chapter 5, June 2002.
[ PDF
| book website ]
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"Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines"
Seongmoo Heo, Kenneth Barr, Mark Hampton, and Krste Asanović
29th International Symposium on Computer Architecture (ISCA-29),
Anchorage, AK, May 2002.
[ PDF |
conference ]
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"Exposing Datapath Elements to Reduce Microprocessor Energy Consumption"
Mark Hampton
S.M. Thesis, Massachusetts Institute of Technology, June 2001.
[ PDF
]
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