Memory System Micro Optimization

Memory systems have become the dominant consumer of power and latency in todays microprocessor. The Memory System Micro Optimization project seeks to make memory systems more efficient by using application specific information. The underlying mechanisms of the memory system are exposed to the compiler. The compiler then extracts information from each program and uses this information to construct the most efficient possible memory operations. We are applying memory system micro optimization to improve the efficiency of data caches, instruction caches, and memory dependence speculation systems.

Papers

• Matthew Frank, Walter Lee and Saman Amarasinghe, A Software Framework for Supporting General Purpose Applications on Raw Computation Fabrics, MIT-LCS Technical Memo MIT-LCS-TM-619, July 20, 2001.
  [pdf] [Postscript] [Compressed postscript]

• Csaba Andras Moritz, Matthew Frank, and Saman Amarasinghe, FlexCache: A Framework for Flexible Compiler Generated Data Caching, The 2nd Workshop on Intelligent Memory Systems, Boston, MA, November 12, 2000.
  [pdf] [Postscript] [Compressed postscript]

• Csaba Andras Moritz, Matthew Frank, Walter Lee, and Saman Amarasinghe, Hot Pages: Software Caching for Raw Microprocessors, MIT-LCS Technical Memo LCS-TM-599, November 5, 1999.
  [pdf] [Postscript] [Compressed postscript]

• Rajeev Barua, Walter Lee, Saman Amarasinghe, and Anant Agarwal, Maps: A Compiler-Managed Memory System for Raw Machines, Proceedings of the Twenty-Sixth International Symposium on Computer Architecture (ISCA-26), Atlanta, GA, June, 1999.
  [pdf] [postscript] [compressed postscript]

• J. Babb, M. Rinard, A. Moritz, W. Lee, M. Frank, R. Barua, and S. Amarasinghe, Parallelizing Applications Into Silicon, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines '99 (FCCM '99), Napa Valley, CA, April 1999.
  [pdf] [postscript] [compressed postscript]

• M. Frank, C. A. Moritz, B. Greenwald, S. Amarasinghe, and A. Agarwal, SUDS: Primitive Mechanisms for Memory Dependence Speculation, MIT/LCS Technical Memo LCS-TM-591, January 6, 1999.
  [pdf] [Postscript] [Compressed postscript]

• W. Lee, R. Barua, M. Frank, D. Srikrishna, J. Babb, V. Sarkar, and S. Amarasinghe, Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine, Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), San Jose, CA, October 4-7, 1998.
  [pdf] [Postscript] [Compressed postscript]

• E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal, Baring It All to Software: Raw Machines, IEEE Computer, September 1997, pp. 86-93.
  [pdf] [Postscript] [Compressed postscript]

Theses

• Kevin Wilson, Integrating Data Caching into the SUDS Runtime System, MEng Thesis, MIT EECS, May 2000.
  [pdf] [Postscript] [Compressed Postscript]

• Rajeev Barua, Maps: A Compiler-Managed Memory System for Software-Exposed Architectures, PhD Thesis, MIT EECS, January 2000.
  [pdf] [postscript] [compressed postscript]

• Benjamin Greenwald, A Technique for Compilation to Exposed Memory Hierarchy, SM Thesis, MIT EECS, September 1999.
  [pdf]

• Jason Miller, Software Based Instruction Caching for the RAW Architecture, MEng Thesis, MIT EECS, May 1999.
  [pdf] [Postscript] [Compressed Postscript]

People

Professors

• Saman Amarasinghe
• Csaba Andras Moritz

Students

• Jonathan Babb
• Benjamin Greenwald
• Matthew Frank
• Jason Miller
• Walter Lee
• Vladimir Kiriansky

Alumn[i/ae]

• Rajeev Barua
• Kevin Wilson

Related

• Much of our work has been done in the context of the MIT Raw project.
• Many of us are members of the Commit group at MIT.
• Some of our ideas are being applied by the SCALE group to improve power and energy consumption.

$Date: 2001/07/24 21:21:57 $