More Virtual Wires:
Background
While research and development on Alewife continued in 1993, ideas by Jonathan Babb and Anant Agarwal sprung up in doing a specialized type of logic emulation. As logic can be simulated in software, it can also be simulated in specialized hardware systems. This simulation with hardware assistance is called logic emulation. One method of logic emulation can be realized through the use of FPGAs (Field Programmable Gate Array).
One to one allocation of emulation signals (logical wires) does not exploit available off chip bandwidth because: 1) emulation clock frequencies are one to two orders of magnitude lower than the potential clocking frequency of the FPGA technologies, and 2) all logical wires are not active simultaneously.
Thus, although the FPGA partitions are pin limited, each pin is severly underutilized.
Virtual Wires
By pipelining and multiplexing physical wires, we can create virtual wires to increase useable bandwidth. A virtual wire represents a single connection between a logical output on one FPGA partition and logical input on another FPGA partition. The physical connection is composed of one or more intermediate physical wires which may be shared in a time multiplexed fashion, by storing logical outputs in shift registers, and shifting them into shift registers on the receiving FPGA. By having shift loops on the sending and receiving end in an
organized manner with a physical wire between FPGAs, one can think of each shift register being a pin on the FPGA. Thus overcomming the pin limitations of
the FPGA device and allowing the user to have higher than previously possible
intercommunication between FPGAs. The new limitation becomes the registers on the chip; however, there are more registers available than there are pins availible on a given FPGA.
(to be continued)
Current Research
As the virtual wires system has successfully emulated several designs like sparcle and palindrome,
there has been additional research in using the virtual wires system for
virtual computing. We have been able to create a framework whereby hardware
subroutines can be downloaded onto the virtual wires board, and C programs
can call subroutines on the virtual wires board. This provides the ability
to perform high computation type procedures at hardware speeds. We are
currently limited to a serial interface and thus, while the routines on
the FPGAs easily outperform their software counterparts, the IO to and from the board is the major bottleneck and thus, few procedures show an overall system implementation speedup.
We are also researching and developing the readback/debugging capabilities of the FPGA based virtual wires system. This involves being able to upload the states or signals of the FPGAs on the board, and correlating these signals with the netnames of the users design. Additionally, we will be implementing some basic debugging features like breakpoints and watches into the system. This research is targeted for completion in November.
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