#========================================================================= # Spongepaint standard cell datapath generator configuration file # #------------------------------------------------------------------------- OPTIONS_SECTION #------------------------------------------------------------------------- dpathName = incdec8 bitWidth = 32 firstDataTrack = 1 lastDataTrack = 8 spTechFile = incdec8.sptech logFile = incdec8.log scLeafLayoutFile = /home/cad/tsmc/18/artisan/sc/gds2/tsmc18.gds2 scLeafVerilogFile = /home/cad/tsmc/18/artisan/sc/verilog/tsmc18.v #------------------------------------------------------------------------- BUILDERS_SECTION #------------------------------------------------------------------------- # List builders here with the leftmost builder first. Each builder # takes various arguments so make sure you have them correct. spPowerSCBuilder leftpower 2 FILL1 spConstantSCDpathBuilder incConst 0x00000001 TIELO TIEHI spSimpleSCDpathBuilder inv INVX2 A,Y spConstantSCDpathBuilder zeroConst 0x00000000 TIELO TIEHI spMuxSCDpathBuilder muxA 4 MX4X1 spMuxSCDpathBuilder muxB 4 MX4X1 spRippleAdderSCDpathBuilder adder ADDFX1 spSimpleSCDpathBuilder addReg EDFFTRX1 D,Q *CK,E,*RN spSimpleSCDpathBuilder compReg EDFFTRX1 D,Q *CK,E,*RN spCmpSCDpathBuilder compare XOR2X1 OR4X1 OR2X1 FILL1 spPowerSCBuilder rightpower 2 FILL1 #------------------------------------------------------------------------- NETLIST_SECTION #------------------------------------------------------------------------- # List labels to promote and power nets before the actual netlist. You # can specify promotion labels using this syntax: # # promoteLabel # promotePowerNets # promoteLabel xmuxA S0 add_selA_0_ promoteLabel xmuxA S1 add_selA_1_ promoteLabel xmuxB A datain promoteLabel xmuxB S0 add_selB_0_ promoteLabel xmuxB S1 add_selB_1_ promoteLabel xadder CI cin promoteLabel xadder CO cout promoteLabel xaddReg E add_reg_en promoteLabel xcompReg E comp_reg_en promoteLabel xcompare Y neq promotePowerNets VDD VSS joinNets xaddReg CK clk joinNets xcompReg CK clk joinNets xaddReg RN reset joinNets xcompReg RN reset net addA 32 net addB 32 net add_out 32 wire xincConst.Y xinv.A wire xincConst.Y xmuxA.A wire xinv.Y xmuxA.B wire xzeroConst.Y xmuxA.C wire xzeroConst.Y xmuxA.D wire xmuxA.Y addA wire xaddReg.Q xmuxB.B wire xzeroConst.Y xmuxB.C wire xzeroConst.Y xmuxB.D wire xmuxB.Y addB wire addA xadder.A wire addB xadder.B wire xadder.S add_out wire add_out xaddReg.D wire xmuxB.A xcompReg.D wire add_out xcompare.A wire xcompReg.Q xcompare.B # # END # (Make sure there is a new line at the end of the file!) #