*****************************************************************************
*** Spice driver for worst case delay in 32 bit counter unit

.lib log018.l TT 

.param pvdd=1.8v
.option nomod post brief

.trans 0.01ns 70ns uic
.temp 25

.include incdec-noeffw.sp

vdd PWR 0 pvdd

vclk     clk     0 PU( 0v pvdd 5ns 0.1ns 0.1ns 5ns 10ns )
vreset   reset   0 PU( 0v pvdd 7ns 0.1ns 0.1ns 100ns 500ns )

vdatain_0_  datain_0_  0 0 
vdatain_1_  datain_1_  0 0 
vdatain_2_  datain_2_  0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_3_  datain_3_  0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_4_  datain_4_  0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_5_  datain_5_  0  PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_6_  datain_6_  0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_7_  datain_7_  0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_8_  datain_8_  0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_9_  datain_9_  0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_10_ datain_10_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_11_ datain_11_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_12_ datain_12_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_13_ datain_13_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_14_ datain_14_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_15_ datain_15_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_16_ datain_16_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_17_ datain_17_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_18_ datain_18_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_19_ datain_19_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_20_ datain_20_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_21_ datain_21_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_22_ datain_22_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_23_ datain_23_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_24_ datain_24_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_25_ datain_25_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_26_ datain_26_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_27_ datain_27_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_28_ datain_28_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_29_ datain_29_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_30_ datain_30_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )
vdatain_31_ datain_31_ 0 PWL( 0ns 0 6.9ns 0 7.0ns 0 16.9ns 0 17ns pvdd )


vadd_selA_0_ add_selA_0_ 0 PWL( 0ns pvdd 26.9ns pvdd 27ns 0 )
vadd_selA_1_ add_selA_1_ 0 PWL( 0ns pvdd 26.9ns pvdd 27ns 0 )
vadd_selB_0_ add_selB_0_ 0 PWL( 0ns pvdd 16.9ns pvdd 17.0ns 0 26.9ns 0 27ns pvdd )
vadd_selB_1_ add_selB_1_ 0 PWL( 0ns pvdd 16.9ns pvdd 17.0ns 0 26.9ns 0 27ns 0 )
vadd_reg_en  add_reg_en  0 PWL( 0ns 0 16.9ns 0 17.0ns pvdd )
vcomp_reg_en comp_reg_en 0 PWL( 0ns 0 6.9ns 0 7.0ns pvdd 16.9ns pvdd 17ns 0 )

vcin cin 0 0

xincdec 0 datain_31_ datain_30_ datain_29_ datain_28_
+	 datain_27_ datain_26_ datain_25_ datain_24_ datain_23_
+	 datain_22_ datain_21_ datain_20_ datain_19_ datain_18_
+	 datain_17_ datain_16_ datain_15_ datain_14_ datain_13_
+	 datain_12_ datain_11_ datain_10_ datain_9_ datain_8_
+	 datain_7_ datain_6_ datain_5_ datain_4_ datain_3_ datain_2_
+	 datain_1_ datain_0_ PWR clk add_reg_en reset comp_reg_en
+	 add_selB_0_ add_selB_1_ neq add_selA_0_ add_selA_1_ cin cout incdec

.end