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I am a former member of the commit group, part of the Computer Architecture Group within MIT's Computer Science and Artificial Intelligence Laboratory. My advisor was Saman Amarasinghe. For my PhD work we applied machine-learning
techniques to compilation. You can find a description of our work here. For my Master's thesis, we designed and implemented a compiler that infers bitwidth information from a high level description of a program. Check out this work here. |
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Theses |
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Automating the Construction of Compiler
Heuristics Using Machine Learning.
PhD thesis. Massachusetts Institute of Technology. May
2006. (pdf). |
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Bitwise: Optimizing Bitwidths
Using Data-Range Propagation.
Master's thesis. Massachusetts Institute of Technology.
May 2000. (ps, pdf). |
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Papers |
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M. Stephenson, S. Amarasinghe. Predicting
Unroll Factors Using Supervised Classification. In Proceedings of International Symposium on Code Generation
and Optimization. |
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D. Puppin, M. Stephenson, W. Lee, S. Amarasinghe. Convergent
Scheduling. In Journal of
Instruction-Level Parallelism. Volume 6, September 2004 (pdf). |
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D. Puppin, M. Stephenson, S. Amarasinghe, U. O'Reilly, M. Martin. Adapting Convergent Scheduling
Using Machine Learning. In Proceedings of the 16th International
Workshop on Languages and Compilers for Parallel Computing, |
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M. Stephenson, M. Martin, U. O'Reilly, and S. Amarasinghe. |
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M. Stephenson, U. O'Reilly, M. Martin, and S. Amarasinghe. Genetic
Programming Applied to Compiler Heuristic Optimization. In Proceedings
of the 6th European Conference on Genetic Programming, |
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M. Stephenson, J.
Babb, and S. Amarasinghe.
Bitwidth Analysis with Application to Silicon
Compilation. In Proceedings of the SIGPLAN conference on
Programming Language Design and Implementation, |
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