Things Dave has found out that he thinks can help the world if other people could find a web page about
- How to set up X Windows tunelling via ssh
- Synthesizable Verilog Programming Conventions and Resources
Graduate Research
Master's Thesis
In my Master's Thesis I compared how differing architectures (ASIC/FPGA/P4/Raw) are able to handle Bit-level Communication Processing in terms of performance and performacne per area. This was done with the goal of figuring out what computer architects should build in the future to handle a mix of general purpose computation and Bit-level processing normally found in helper chips. I also outline one possible general purpose computing architecture that is influenced by my findings.Download my Master's Thesis, "Architectural Implications of Bit-level Computation in Communication Applications" (PDF...814K, PS better for printing...39MB). Finished September 3, 2002 in partial fullfillment of the requirements for the degree of Master of Science in Electrical Engineering and Computer Science at MIT. Also here is a BibTeX entry for it.
Constructing Virtual Architectures on a Tiled Processor -- Presented at CGO 2006
In this work, I constructed a parallel dynamic binary translation system that allows the execution of x86 binaries on the MIT Raw Prototype Processor. This work presents several new techniques in acceleration of dynamic binary translation on tiled and multi-core processors.Download my CGO 2006 paper, "Constructing Virtual Architectures on a Tiled Processor" (PDF...172K). You can also download the presentation (PPT...2.6MB). Also here is a BibTeX entry for it.
Work Contact Information
David Wentzlaff
32 Vassar St.
Room 32-G742
Cambridge, MA 02139
(617)253-6028
wentzlaf AT cag.csail.mit.edu
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